During the testing phase of a design, it is often very helpful to be able to test the IC's in your ciruit. One of the best tools for this is a JTAG connector which can perform boundary scans on the IC to help debug a problem or to ensure efficiency. The boundary scan is a method for testing the interconnects on PCB's or sub blocks within an IC. It is also used to analyze pin states, measure voltgae or analyze sub-bloks inside an IC.
Boundary Scan is often referred to as JTAG (from the Joint Test Action Group) which is a specification for boundary scan. A supplement for this contains a description of the Boundary Scan Descrition Language (BSDL). This JTAG interface is often accessed using a 5 pin header (offboard connector). This header will have the following connections:
1) TDI - Test Data Input
2) TDO - Test Data Output
3) TRST - Test Reset
4) TCK - Test Clock Input
5) TMS - Test Mode Select
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