Yesterday and today I've been working on a schematic involving Altera's Stratix IV FPGA. This is one complicated device to work on.
I'm just doing simple stuff with it at the moment, but very necessary work. I have to go through about 1500 pins, ensure they have the correct pin names, pin numbers and that they then have the correct net names and connected to the correct offpage, if they are connected to an offpage of course. This is a long and boring task, but like I said earlier, it's a big have to do.
Other checks involve checking the voltage reference points and voltage inputs are correct. I'll also have to check the TTL levels on each input/output and make sure they're transmitting at the correct voltage level as well.
With regards voltage inputs, decoupling is a major factor. I've tried to search the web and through numerous books to try and find out whats the best rule of thumb for decoupling. So far, I haven't had much luck, other than 1 x 0.1uF capacitor for every two VCC pins and then one tantalum capacitor. Different voltages need their own seperate decoupling as well.
That's enough from me now, better get back to work, laters.
Friday, 9 January 2009
Wednesday, 7 January 2009
JTAG Boundary Scan
During the testing phase of a design, it is often very helpful to be able to test the IC's in your ciruit. One of the best tools for this is a JTAG connector which can perform boundary scans on the IC to help debug a problem or to ensure efficiency. The boundary scan is a method for testing the interconnects on PCB's or sub blocks within an IC. It is also used to analyze pin states, measure voltgae or analyze sub-bloks inside an IC.
Boundary Scan is often referred to as JTAG (from the Joint Test Action Group) which is a specification for boundary scan. A supplement for this contains a description of the Boundary Scan Descrition Language (BSDL). This JTAG interface is often accessed using a 5 pin header (offboard connector). This header will have the following connections:
1) TDI - Test Data Input
2) TDO - Test Data Output
3) TRST - Test Reset
4) TCK - Test Clock Input
5) TMS - Test Mode Select
Boundary Scan is often referred to as JTAG (from the Joint Test Action Group) which is a specification for boundary scan. A supplement for this contains a description of the Boundary Scan Descrition Language (BSDL). This JTAG interface is often accessed using a 5 pin header (offboard connector). This header will have the following connections:
1) TDI - Test Data Input
2) TDO - Test Data Output
3) TRST - Test Reset
4) TCK - Test Clock Input
5) TMS - Test Mode Select
2 wire device interfaces
I2C (Inter Integrated Circuit)
SMBus (System Management Bus)
I2C is a computer bus invented by Philips to attach low speed peripherals to a motherboard or an embedded system. SMBus is a subset of I2C that has stricter electrical and convention rules. SMBus is used to promote robustness and interoperability.
I2C and SMBus use only two bidirectional open-drain lines, Serial Data(SDA) and Serial Clock (SCL), (DAT and CLK for SMBus). Both have to be pulled up externally. Nominal voltage pull ups are +3.3V and +5V. Both I2C and SMBus operate with a master and slave address to communicate with specific devices in a circuit. The number of devices on any line depends on address space and the capacitance load. Maximum capacitance is 400pF which restricts communication to a few meters.
The I2C and SMBuses are similar and compatible with each other. They can both communicate with each other over clock rates below 100KHz, however the I2C can operate at 400KHz and 2MHz as well.
I could go into clock diagrams here and explain the more intricate parts of both, but I think I'll leave that to a later date.
SMBus (System Management Bus)
I2C is a computer bus invented by Philips to attach low speed peripherals to a motherboard or an embedded system. SMBus is a subset of I2C that has stricter electrical and convention rules. SMBus is used to promote robustness and interoperability.
I2C and SMBus use only two bidirectional open-drain lines, Serial Data(SDA) and Serial Clock (SCL), (DAT and CLK for SMBus). Both have to be pulled up externally. Nominal voltage pull ups are +3.3V and +5V. Both I2C and SMBus operate with a master and slave address to communicate with specific devices in a circuit. The number of devices on any line depends on address space and the capacitance load. Maximum capacitance is 400pF which restricts communication to a few meters.
The I2C and SMBuses are similar and compatible with each other. They can both communicate with each other over clock rates below 100KHz, however the I2C can operate at 400KHz and 2MHz as well.
I could go into clock diagrams here and explain the more intricate parts of both, but I think I'll leave that to a later date.
Infiniband
Today, I'm working with Mellanox's fourth generation adapter device. It's a ConnectX device which has support for virtual protocol interconnect, providing both infiniband and ethernet network interfaces. Eek, that sounds long and complicated. At the moment, it is for me but I'll get the hang of it, I have to.
So, whats inifiniband? It's a swtiched fabric communications link primarily usedin high-performance computing. It's scalable, which means you build a load of them together and connect them all up for greater speeds. The InfiniBand architecture specification defines a connection between processor nodes and high performance I/O nodes such as storage devices. It is a superset of the Virtual Interface Architecture.
I'll have more for you later, now I gotta read the datasheet and figure this all out, then compare it against our very own schematics and log bugs through our bug system, powered by Axosoft's OnTime.
Laters
So, whats inifiniband? It's a swtiched fabric communications link primarily usedin high-performance computing. It's scalable, which means you build a load of them together and connect them all up for greater speeds. The InfiniBand architecture specification defines a connection between processor nodes and high performance I/O nodes such as storage devices. It is a superset of the Virtual Interface Architecture.
I'll have more for you later, now I gotta read the datasheet and figure this all out, then compare it against our very own schematics and log bugs through our bug system, powered by Axosoft's OnTime.
Laters
Tuesday, 6 January 2009
Decoupling
Another post today, you'd think I'd leave this thing alone wouldn't you.
Anyways, I'm currently looking at the power decoupling for this QuadPHY I mentioned earlier today. Decoupling is simply a way of preventing undesired coupling between subsystems via the power supply connections. To put simply, if you have two devices working off the 2.5V power plane, you don't want one to start sucking power, leaving the other device short on current. So to prevent this, we connect localized capacitors close to the power leads of integrated circuits to act as a small localized energy reservoir. This will supply the circuit with current during transient, high current demand periods, preventing voltage being pulled down from momentary current loads.
To construct these wells, we use a number of capacitors in series. A surface mounted, ceramic multi layer chip capacitors (SMT, MLCC) are ideal for this situation. However greater capacitance may be needed depending on the voltages and currents being applied.
The rule of thumb with voltage rating for a capacitor is usually between 1.5 to 2 times the voltage being used (this is specified in the Military Handbook 217F. It's freely available online, but it still sounds cool when you're reading official military documents). So if you have a circuit that draws 3V, then it's best to use a voltage rating of 4.5V. Common rated caps come in 6.3V though, so you'd probably use this one instead. The temperature coefficients are very important when choosing the capacitor as well. X5R and X7R are the better quality caps to go for. They're the best priced too. But I'm not going to go into Temperature coefficients here, thats way complicated and not interesting. You can find out more about it on Wikipedia.
Anyways, I'm currently looking at the power decoupling for this QuadPHY I mentioned earlier today. Decoupling is simply a way of preventing undesired coupling between subsystems via the power supply connections. To put simply, if you have two devices working off the 2.5V power plane, you don't want one to start sucking power, leaving the other device short on current. So to prevent this, we connect localized capacitors close to the power leads of integrated circuits to act as a small localized energy reservoir. This will supply the circuit with current during transient, high current demand periods, preventing voltage being pulled down from momentary current loads.
To construct these wells, we use a number of capacitors in series. A surface mounted, ceramic multi layer chip capacitors (SMT, MLCC) are ideal for this situation. However greater capacitance may be needed depending on the voltages and currents being applied.
The rule of thumb with voltage rating for a capacitor is usually between 1.5 to 2 times the voltage being used (this is specified in the Military Handbook 217F. It's freely available online, but it still sounds cool when you're reading official military documents). So if you have a circuit that draws 3V, then it's best to use a voltage rating of 4.5V. Common rated caps come in 6.3V though, so you'd probably use this one instead. The temperature coefficients are very important when choosing the capacitor as well. X5R and X7R are the better quality caps to go for. They're the best priced too. But I'm not going to go into Temperature coefficients here, thats way complicated and not interesting. You can find out more about it on Wikipedia.
Running Car as water hybrid
Been researching running my car with water. Not completely with water. To be honest, not with water at all. Been looking into using this convertor which uses baking soda as a catalyst in an electrolytic reaction which produces a hydroxy gas. Which I'm told is Hydrogen and Oxygen gas with all the strength of water and none of the instability and explosiveness as they are on their own as gases. Then this is simply pumped into the cylinder as it goes down.
The theory behind it is that in a combustion engine, when the cylinder descends, the fuel fills in, but there's an inefficiency her in that it doesn't fill up to the full and as a result mixes air into it, causing dirt build up. By injecting this hydroxy, it can increase efficiency by 33% and produce less emissions as there's less carbon and dirt in the mix, producing steam from the emission of the hydroxy.
How right this is and how accurate is still to be determined. I like the idea but I'm way off fully understanding it and applying it and possibly wrecking my car engine. Still though, I enjoy the idea and want to learn more about it.
Check out runcar-onwater.com, seems a bit dodgy, but an interesting possibility.
The theory behind it is that in a combustion engine, when the cylinder descends, the fuel fills in, but there's an inefficiency her in that it doesn't fill up to the full and as a result mixes air into it, causing dirt build up. By injecting this hydroxy, it can increase efficiency by 33% and produce less emissions as there's less carbon and dirt in the mix, producing steam from the emission of the hydroxy.
How right this is and how accurate is still to be determined. I like the idea but I'm way off fully understanding it and applying it and possibly wrecking my car engine. Still though, I enjoy the idea and want to learn more about it.
Check out runcar-onwater.com, seems a bit dodgy, but an interesting possibility.
Snowboarding Chamonix
Am heading to Chamonix on Saturday 17th January. Really looking forward to it, haven't been boardin in ages and as some of you know, Kilternan just doesn't do it.
Goin for a week with one of my best mates, John McGuinness. Staying Chalet Chocolat, just a few minutes outside of Chamonix. It's going to be amazing!
Since Fiona's death (Fiona being my last snowboard, an F2 Floater, not an amazing board, but we got through so much), I've lost all want to board, but hopefully this trip should rekindle that age old love that I've had for so long now.
Check out Chalet Chocolat on Rude Chalet's website.
Goin for a week with one of my best mates, John McGuinness. Staying Chalet Chocolat, just a few minutes outside of Chamonix. It's going to be amazing!
Since Fiona's death (Fiona being my last snowboard, an F2 Floater, not an amazing board, but we got through so much), I've lost all want to board, but hopefully this trip should rekindle that age old love that I've had for so long now.
Check out Chalet Chocolat on Rude Chalet's website.
Swizzling
What the hell is swizzling?
I've found mention of bit swizzling for this QuadPHY and google won't tell me.
Help me!
I've found mention of bit swizzling for this QuadPHY and google won't tell me.
Help me!
XAUI to XGMII
I'm currently working on a 10GX QuadPHY with 4 x 1.2 to 3.2 Gbit/s Quad, Fully Redundant, XAUI to XGMII, 10 Gigabit Ethernet/Fibre Channel Physical Layer Device.
It's difficult to understand but I'm working my way through it.
Whats XAUI you say?
Pronounced 'zowie', is a standard for connecting 10 Gigabit Ethernet PHY to an Ethernet MAC on a PCB. XAUI = 10X Attachment Unit Interface. XAUI connects the PHY to the backplane of the PCB.
What's XGMII you say?
A 72-pin 10 Gigabit Media Independent Interface. This is a standard for connecting full duplex 10GbE ports to each other and to other electronic devices. Composed of 2 x 32bit datapaths (Rx and Tx) and 2 x 4bits control flows (Rxc and Txc), operating at 156.25MHz. With a multiplier of 20X, 3.125Gbit/s transfers are possible. The XGMII connects the PHY to the FPGA.
PHY = Physical Layer
MAC = Media Access Control Layer
FPGA = Field Programmable Gate Array
PCB = Printed Circuit Board
It's difficult to understand but I'm working my way through it.
Whats XAUI you say?
Pronounced 'zowie', is a standard for connecting 10 Gigabit Ethernet PHY to an Ethernet MAC on a PCB. XAUI = 10X Attachment Unit Interface. XAUI connects the PHY to the backplane of the PCB.
What's XGMII you say?
A 72-pin 10 Gigabit Media Independent Interface. This is a standard for connecting full duplex 10GbE ports to each other and to other electronic devices. Composed of 2 x 32bit datapaths (Rx and Tx) and 2 x 4bits control flows (Rxc and Txc), operating at 156.25MHz. With a multiplier of 20X, 3.125Gbit/s transfers are possible. The XGMII connects the PHY to the FPGA.
PHY = Physical Layer
MAC = Media Access Control Layer
FPGA = Field Programmable Gate Array
PCB = Printed Circuit Board
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