The day after Pancake Tuesday

Right, well I was supposed to go to the Engineer's Ireland member's information meeting yesterday. Needless to say I didn't go. I had a chat with a colleague here in work, he informed me that Engineer's Ireland is geared more towards civil and constructional engineering rather than Electronic Engineering. I don't think I want to pay for membership to receive periodicals on how to mix cement and lay tarmacadam. When will I ever use that?

So instead, I went home, made pancakes and read my VHDL book. Much more productive I think. See my recipe blog at Pyrolith's Recipes!

I've decided I'm going to join the American IEEE instead. They seem more geared to my industry and they have a lot more information and benefits for joining. All I hope I can do now is get the company to pay for my subscription. Now that'd be nice alright.

Pancake Tuesday

Yay Pancakes!
I hope I get a chance to eat some pancakes today. Busy day today.

Heading to the Engineer's Ireland Information meeting tonight. I'm looking to find out what are the advantages of being a member.

When:	16/02/2010 From 6.00 PM until 8.00 PM
Where:	Engineers Ireland 22 Clyde Road Ballsbridge Dublin 4 Ireland

For more information regarding this event please visit:
http://members.engineersireland.ie/events/event_details.asp?id=93192


By the way, lemon and sugar pancakes all the way!!

AdSense gone, blog writing for company

I've removed AdSense after reading in an article about blogging. Apparently the whole adverts on your blog make it look tacky, unappealing and cheap. Never thought of it like that, on a second look though, my page looked like all those without the ads in the first place. So I figured, remove it, give the page a chance.

I'm currently writing up some draft information for writing for my companies blog site. We've currently got nothing at the moment. Hopefully I can write enough information each week to keep any readers that we may get interested. My only worry is the sensitive nature of writing a company blog. Can't go saying anything that could harm our reputation, while at the same time, not making blatant lies about how amazing we are. There's nothing wrong with a few delightful adjectives around the place, in moderation of course. Will post up the link here if I get it and my proposal is accepted and when it is posted up online.

Hopefully I'll get more readers and experience in this whole blogging phenomena and may even do this blog up properly as well. Sure we'll see what happens.

Take it easy out there in the blogosphere ;)

Channel Interleave and Rank Interleaving

Been having a look into Channel and Rank Interleaving. Check out the explanations below for further explanations of what they are. (Explanation copied from http://www.anandtech.com/mb/showdoc.aspx?i=3519&p=5)

Channel Interleave: Higher values divide memory blocks and spread contiguous portions of data across interleaved channels, thereby increasing potential read bandwidth as requests for data can be made to all interleaved channels in an overlapped manner. For benchmarking purposes when using three memory modules, a 4-way interleave may surpass the scoring performance of setting 6-way interleave depending on the benchmark and operating system used (32-bit vs. 64-bit). We did find however that a 6-way interleave was capable of a higher overall BCLK for Super PI 32M than using a 4-way interleave setting (unless of course you run single- or dual-channel and appropriate channel interleaving thus decreasing load upon the memory controller).

Rank Interleave: Interleaves physical ranks of memory so that a rank can be accessed while another is being refreshed. Performance gains again depend on the benchmark in question. For 24/7 systems using triple-channel memory configurations there is no advantage to setting this value below 4 while Channel Interleave should be left at 6 for best overall system performance.

The rest of the memory parameters pretty much default to optimum levels; moving away from these values can in some instances make matters worse in terms of system stability rather than performance. The current BIOS defaults are just about optimal for most overclocking. The highest performance advantage comes from changing the primary memory timings. There's little to no gain in fiddling with any of the secondary timing ranges, other than moving tRFC out to a value of 88 or more if running 12GB (6x2GB) of memory.

So to conclude, Channel and Rank Interleaving settings should be enabled and set to the highest on the board as possible for the greatest memory performance. Nuff said :D

SPD Data

Had a late night here in work last night and tried to get to grips with SPD Data. When I say SPD data, specifically I'm talking about the SPD data for DDR3 DIMM's. What's SPD data you say? It's a table of the timings and settings saved in an EEPROM on the DIMM (Dual Inline Memory Module) module itself. SPD (Serial Presence Detect) is usually a small EEPROM (Electrically Erasable Programmable Read-Only Memory) usually an Atmel 24C02. This is a 2Kb part 8 pin SOIC (Small Order Integrated Circuit) which is enough to store all the settings for your DIMM module.

Using the SPD Tool I mentioned in my last blog entry, you can customise the exact timings on your DIMM, unfortunately though at the moment, it only supports DDR2 and below. The other way to do it is through your BIOS.


Here's a great website which explains each byte in little detail. You can work it out from there. It covers DDR3, DDR2 and the older DDR.

Understanding DDR3 Serial Presence Detect (SPD) Table

DDR2 DIMM SPD Definition

There's also a few interesting publications in there about how DDR3 memory works and an informative one on how to reball and recover DDR2 memory chips. Obviously the tools used in reballing are only used in manufacturing plants, but it's still interesting to see.

How DDR3 Memory Works ?
How to Reball and Recover DDR2 Memory Chips

SPD Tool

Found an interesting tool for reading SPD data from your DIMM's on your PC. Was looking for a tool that could do this for a system we're working on, however it doesn't support DDR3 or ICH10 access at the moment, so until then I'll have to find another way to access this information.

SPD TOOL 0.63

If anyone has a tool or knows of a tool for reading or writing SPD data for DDR3 DIMM modules, supporting an ICH10? I'd be very very appreciative!

Created a small RS232 Transceiver yesterday

On a current project we're working on, we had a serial port output which came from the BMC, but there was no RS232 to level shift the TTL levels. In this design, the RS232 transceiver is on the adjoining system which connects to this serial port.

So for testing purposes, to test this serial port we needed to either invest in a special cable with it all built in or make one ourselves from locally available parts. Unfortunately we weren't able to wait for the arrival from Farnell of the USB to TTL cable from FTDI (TTL-RS232-3V3). So I drove down to Maplin and picked me up a small Maxim RS232 transceiver (MAX3232CPE), 5 0.1uF ceramic disc caps and a male and female serial port header. Back in the labs, I snapped off a bit of unused bread-board, soldered in the part, cut the tracks beneath the device to isolate the pins on either side. Attached the 0.1uF caps, wires and I got 3V3 from the front of a capacitor on the actual system itself. Attached the thing up and lo and behold... it didn't work :(

I had the TX and Rx the wrong way around. I was using a crossover cable which swaps the Tx and Rx when going from my device to the Host PC. Once swapped, the yoke works proper. I haven't tested to see how clean the signals are yet, but it should work like a beauty.

The easy part was knowing where to hook up the caps and what to solder to where, it's all freely available on Maxim-IC's website MAX3222-MAX3241 DATASHEET (PDF).
See page 12 for the exact circuit I used. If using a different input voltage to 3V3, then check out table 2.