Stratix IV FPGA

Yesterday and today I've been working on a schematic involving Altera's Stratix IV FPGA. This is one complicated device to work on.
I'm just doing simple stuff with it at the moment, but very necessary work. I have to go through about 1500 pins, ensure they have the correct pin names, pin numbers and that they then have the correct net names and connected to the correct offpage, if they are connected to an offpage of course. This is a long and boring task, but like I said earlier, it's a big have to do.
Other checks involve checking the voltage reference points and voltage inputs are correct. I'll also have to check the TTL levels on each input/output and make sure they're transmitting at the correct voltage level as well.
With regards voltage inputs, decoupling is a major factor. I've tried to search the web and through numerous books to try and find out whats the best rule of thumb for decoupling. So far, I haven't had much luck, other than 1 x 0.1uF capacitor for every two VCC pins and then one tantalum capacitor. Different voltages need their own seperate decoupling as well.

That's enough from me now, better get back to work, laters.